1. Field
Various features relate, generally, to an integrated device and, more specifically, to an integrated device including an interconnect surrounding another interconnect and providing a connection to ground.
2. Background
FIG. 1 illustrates a first cross-sectional view of a conventional integrated device 100 (e.g., a package-on-package (PoP) integrated device). The conventional integrated device 100 includes a first package 102 and a second package 104. The first package 102 may include a first substrate 106, a first die 108, a first set of solder balls 110, and a first set of interconnects 112. The first set of solder balls 110 may electrically connect the first substrate 106 with the first die 108. The first substrate 106 may include electrical interconnects 114 and dielectric layers 116. The electrical interconnects 114 may traverse horizontally and/or vertically throughout the first substrate 106 to electrically connect various components contacting the first substrate 106. For example, the electrical interconnects 114 may electrically connect one or more solder balls 110 with one or more interconnects 112. The electrical interconnects 114 may be (at least) partially surrounded by the dielectric layers 116.
The second package 104 may include a second substrate 118, a second die 120, and a second set of solder balls 122. The second set of solder balls 122 may electrically connect the second substrate 118 with the second die 120. The second substrate 118 may include electrical interconnects 124 and dielectric layers 128. A mold 124 may exist in any portion of the space between the first substrate 106 and the second substrate 118. For example, the mold 124 may encapsulate (at least) a portion of the first set of interconnects 112, the first set of solder balls 110, and/or the first die 108.
The first set of interconnects 112 may electrically connect the first substrate 106 with the second substrate 118. Each interconnect 112 may carry a power signal or a ground signal (e.g., a signal connected to ground).
FIG. 2 is a second cross-sectional view of the conventional integrated device 100. The second cross-sectional view illustrated in FIG. 2 is along line 126 in FIG. 1. As illustrated in FIG. 2, a number (e.g., eight) interconnects (e.g., interconnects 1121-8) may electrically connect the first substrate 106 with the second substrate 118. However, such designs have limitations. Any two interconnects carrying a power signal must be separated by at least one interconnect carrying a ground signal; otherwise, the power signals may interfere with each other, thereby causing unacceptable levels of insertion loss and/or isolation. Of the eight interconnects 1121-8 shown in FIG. 2, four alternating interconnects (e.g., interconnects 1121, 1123, 1125, 1127) may carry a power signal while the other four alternating interconnects (e.g., interconnects 1122, 1124, 1126, 1128) may carry a ground signal. Such designs do not allow for a power signal to be transmitted through every interconnect 112 (e.g., all of the interconnects 1121-8). For example, if more than four power signal connections are needed between the first substrate 106 and the second substrate 118, additional interconnects 112 must be added (beyond the eight interconnects 1121-8 already illustrated in FIG. 2). Additional interconnects would undesirably expand the size of the overall conventional integrated device 100. Therefore, existing designs may benefit from enhancements that allow power signals to be conducted through every interconnect while maintaining acceptable levels of isolation and/or insertion loss.